Why pmos is good passer of 1
We call PMOS a strong-1 passer and weak-0 passer. We all know that for an PMOS to have a conduction channel, we apply a negative voltage or 0V to its gate. As long as the gate source voltage V gs is equal to or above its threshold voltage V tp , the PMOS conducts and will give the source voltage at the output.
Now here we consider two cases to understand the reason to call PMOS a strong-1 passer and weak-0 passer. One case with V DD strong-1 applied to source and other with 0V strong-0 applied to source. Click here to register now. Register Log in. JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly. You should upgrade or use an alternative browser. Thread starter Shanthanayaki Start date Jun 26, Status Not open for further replies. Shanthanayaki Newbie level 4. Vice versa why PMOS pass a strong logic 1 and a weak logic 0?. Thanks, Shantha. IanP Advanced Member level 5.
In NMOS the weak transistor is used to generate a high output voltage level or 1 when the strong transistors are turned off. Start on. Show related SlideShares at end. WordPress Shortcode. Next SlideShares. Download Now Download to read offline and view in fullscreen. Download Now Download Download to read offline. Sudhanshu Janwadkar Follow. Keypad Interfacing with Microcontroller.
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But if one of the end of pmos transistor is at VSS, no matter what you do you can not bias other end to VSS, other end can not fall below Vth. You must be logged in to post a comment. So bottom-end in right side transistor can never fall below Vth.
What would happen if the gate is at VDD in both cases?
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